1. Field of the Invention
The present invention relates to a method of forming a trench type isolation layer. More particularly, the present invention relates to a method of forming a trench type isolation layer having a nitride layer liner wherein an upper part is removed.
2. Description of the Related Art
A trench type isolation, developed to overcome a bird""s beak formation problem in a Local Oxidation of Silicon (LOCOS) type isolation, uses a method of filling a trench formed on a substrate with an oxide layer. Accordingly, the bird""s beak problem may be eliminated, but problems such as thermal stress caused by a difference in materials between a substrate and an isolation layer materials and a volume expansion caused by a follow-up oxidation of the substrate adjacent to the isolation layer can be created. To solve these problems, a method of forming a silicon nitride liner on an inner wall of a trench before filling with an oxide layer is developed. The silicon nitride liner acts as a barrier preventing the diffusion of oxygen, thereby preventing a substrate adjacent to a trench from being oxidized in a thermal process and thereby reducing stress.
However, the upper part of the silicon nitride liner is etched during the removal of a silicon nitride layer on an active region, which is used as an etch prevention layer, while forming a trench, thereby causing a dent phenomenon. Subsequently, a problem called xe2x80x98humpxe2x80x99 is created when the etched nitride liner region is filled with a polysilicon gate layer.
Moreover, as the silicon nitride layer has a strong tendency of capturing an electron on a surface, an electron is captured when it is moved along a channel with a silicon nitride liner arranged at both sides of the channel of a Metal Oxide Silicon (MOS) transistor, especially at the thermal oxide layer and silicon nitride layer interface. This phenomenon can change the stream of carriers in the channel region. If the channel has a shallow depth and a large width, these problems decrease. However, in the case of a semiconductor device adopting trench isolation, in order to realize a high degree of device integration, the width of the channel is usually narrow, and hence the silicon nitride liner on both sides of the channel actually affects the stream of carriers, especially, if the main carrier is a hole, when source/drain current flows through the channel, as in the case of a p-channel transistor. The actual stream of the holes increases when an electron is captured in the nitride layer of both sides of the channel, resulting in a kind of a hot carrier effect.
Accordingly, a method of removing a silicon nitride liner in the region of actual depth of channel in order to prevent electron capture is proposed in U.S. Pat. No. 5,940,717. This method is briefly described through the drawings of FIG. 1 through FIG. 4.
Referring to FIG. 1, a trench etching mask pattern 13 is formed by depositing and patterning a silicon nitride layer on a substrate 10 where a pad oxide layer 11 is formed. After forming a trench 21, a thermal oxidation of an inner wall of the trench 21 is performed, thereby forming a thermal oxide layer 15. Then, a thin silicon nitride layer is deposited on the entire surface, thereby forming a trench inner wall liner 17. Subsequently, a photoresist layer 19 fills the trench 21 by a spin coating method.
Referring to FIG. 2, an etch back is applied to the photoresist layer 19 which is filling the trench 21, in order to form a recessed residual photoresist layer 29. Ashing is usually performed in an oxygen plasma atmosphere for etch back of photoresist layer 19. The recess process is performed, until the surface level of the residual photoresist layer 29 remains under an effective depth of channel.
Referring to FIG. 3, the exposed silicon nitride liner 17 on the substrate 10 is removed by etching. Usually, the exposed silicon nitride liner is removed by a dry plasma etching, to a depth, up to which the photoresist is removed.
Referring to FIG. 4, the residual photoresist 29 remaining in the trench is removed, and the trench is filled with an oxide isolation layer 39 by a Chemical Vapor Deposition (CVD) method. A surface of the trench etching pattern 13, comprising a silicon nitride layer on an active region, is exposed by planarization using a Chemical Mechanical Polishing (CMP) method. The silicon nitride layer on the active region is then removed by a follow-up wet etching, thereby completing the formation of the trench type isolation layer 39.
However, this method causes damage due the etching of an adjacent layer (i.e., the layer on top of the active region) during recessing photoresist 19 and removing the silicon nitride liner 17 by etching on an upper part of a trench. An uneven height over an entire substrate is generated while a silicon nitride layer 13 in an active region is partially etched, resulting in an irregular level of a device isolation layer in a CMP step of a CVD oxide layer 39. Also, a current leakage may be easily generated in a device to be formed afterward, if an etching defect is created in a trench sidewall.
It is therefore a feature of an embodiment of the present invention to avoid the conventional problems and prevent the change of a semiconductor device operation by an electron capture of a silicon nitride liner in a trench type isolation and also prevent hot carrier effects.
Another feature of an embodiment of the present invention is to preserve a level of a device isolation layer while partially removing the silicon nitride liner, and to prevent a current leakage adjacent to the trench.
It is yet another feature of an embodiment of the present invention to prevent the oxidation adjacent to a trench by a silicon nitride layer liner, and to provide a method of forming a trench type isolation layer without the problem of a dent.
To provide the above-mentioned features, an embodiment of the present invention provides a method of forming a trench type isolation layer comprising: forming a trench by etching, after forming a trench etching mask pattern on a substrate; forming a silicon nitride liner on an inner wall of the trench; filling the trench with a first buried oxide layer; exposing an upper part of the liner by recessing the first buried oxide layer in the trench with a wet etching process; removing the upper part of the liner using an isotropic etching; and filling the recessed space of the trench with a second buried oxide layer.
Forming a trench etching mask pattern on a substrate is performed by depositing and patterning a silicon nitride layer on a substrate where a pad oxide layer is formed. The method of an embodiment of the present invention further comprises forming a thermal oxide layer, preferably through annealing, for healing etching defects in an inner wall of the trench, between forming a trench and forming a liner. A plasma surface processing step may be performed between forming the liner and filling the trench with a first buried oxide layer to improve gap fill characteristics while reducing dependence of the buried oxide layer on the lower layer. However, as the liner may be easily damaged, the method of an embodiment of the present invention may further comprise depositing a buffer oxide layer like a High Temperature Oxide (HTO) layer by a Low Pressure Chemical Vapor Deposition (LPCVD) over the liner to protect the liner from plasma surface processing damage.
In an embodiment of the present invention, the first buried oxide layer is recessed using a wet process to prevent etching damage to adjacent regions. At this time, it is preferable to perform the recess process until the surface of the first buried oxide layer is lowered below a predetermined depth of channel of a transistor device to be formed afterward, as this may help in preventing electron capture by a silicon nitride liner.
The present invention may be effective in a trench of a p-channel transistor region where electron capture by a silicon nitride liner causes a hot carrier effect. Accordingly, this invention may be preferably applied to p-channel transistor regions.
The present invention may also comprise performing a CMP for a second buried oxide layer and removing the trench etching mask pattern, thereby completing a trench type isolation layer.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.